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FUJITSU SEMICONDUCTOR DATA SHEET
DS06-20209-2E
Semicustom
CMOS
Standard cell
CS86 Series
s DESCRIPTION
The CS86 series of 0.18 m standard cells is a line of CMOS ASICs based on higher integration implemented by introducing wiring pitch reduction technology and on I/O pad placement technology to the conventional CS81 series. The CS86 series has three types of cell sets (CS86MN, CS86MZ, and CS86ML), covering a variety of applications, from portable devices requiring low power consumption to image processors requiring large-scale circuitry and high speed.The three types of cell sets can be contained on one chip, allowing those system LSIs to be implemented which require low power consumption as well as high-speed operation for certain types of processing.
s FEATURES
* Technology : 0.18 m silicon-gate CMOS, 4- to 6-layer wiring The same chip can therefore incorporate the standard transistor cell and the ultrahighspeed or low-leakage process cell together. Supply voltage : +1.8 V 0.15 V (normal) to +1.1 V 0.1 V Junction temperature range : -40 C to +125 C Cell set CS86MN : Offers standard transistor characteristics. Designed as a library for products requiring higher throughputs. CS86MZ : Offers transistor characteristics for ultra high-speed operation. Designed as a library for products that require higher processing speeds than those provided by CS86MN. CS86ML : Offers transistor charactersistics with less leak current. Designed as a library for mobile devices and other products requiring lower power consumption. Cell Specifications : Cell set name CS86MZ CS86MN CS86ML Delay time*1 Power consumption* Leak power*
3 2
* * *
*
70 ps 42.7 nW/MHz 3.922 nW
88 ps 40.1 nW/MHz 0.023 nW
136 ps 38.3 nW/MHz 0.0067 nW
*1 : 2 input NAND cell (low-power type) , F/O = 2, normal load, Power supply voltage 1.8 V, Temperature = +25 C *2 : 2 input NAND cell (low-power type) , F/O = 1, 4 Grid, Power supply voltage 1.8 V, Temperature = +25 C *3 : 2 input NAND cell (low-power type) , F/O = 0, non load, Power supply voltage 1.8 V, Temperature = +25 C (Continued)
CS86 Series
(Continued) * Output buffer cells with noise reduction circuits * Input buffer cells and bidirectional buffer cells with on-chip input pull-up/pull-down resistors * Buffer cells for crystal oscillation circuits * Special interfaces : SSTL2, PCI, P-CML, T-LVTTL, USB 2.0, IEEE1394, and others. * IP macros : CPU (ARM9, FR-V, and others) , DSP, PCI, IEEE1394, USB 2.0, IrDA, PLL, DAC, ADC, and others. * Capable of incorporating compiled cells (RAM/ROM/Register file/Delay line) * Configurable internal bus circuits * Advanced hardware/software co-design environment * Short-term development using Physical Synthesis tool * Low power consumption using Low Power Synthesis tool * Short-term development using a timing driven layout tool * Hierarchical design environment for supporting large-scale circuits * Support for Signal-Integrity * Support for Memory (RAM, ROM) SCAN * Support for Memory (RAM) BIST * Support for Boundary SCAN * Support for path delay test * A variety of package options : QFP, TQFP, LQFP, HQFP, PBGA, FBGA, FLGA, EBGA
2
CS86 Series
s MACRO LIBRARY (Including macros being prepared)
1. Logic cells
* Adder * AND-OR Inverter * Clock Buffer * Latch * NAND * AND * NOR * OR-AND * Scan Flip Flop * ENOR * Boundary Scan Register * Bus Driver * AND-OR * Decoder * NON-Scan Flip Flop * Inverter * Buffer * OR-AND Inverter * OR * Delay Buffer * Selector * EOR * Dummy Clock Buffer * Others
2. IP macro
CPU DSP Peripheral Macro Interface macro Multimedia processing macros Mixed signal macros Compiled macros PLL I/O macro FR-V, ARM9, and others. Communications DSP, DSP for Digital AV, and others. Interval timer, Interruption controller, DMA controller, RTC, Calender, UART, and others. PCI, IEEE1394, USB 2.0, IrDA, and others. JPEG, MPEG 4.0, and others. ADC, DAC, OPAMP, and others. RAM (1 port, 2 port) , ROM, Delay Line, Register file, and others. Analog PLL Compatible with various interface levels between 1.1 V and 5 V; SSTL2, PCI, P-CML, T-LVTTL, USB, IEEE1394, and others.
3
CS86 Series
s COMPILED CELLS
Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CS86 series has the following types of compiled cells. (Note that each macro is different in word/bit range depending on the column type.)
1. Clock synchronous single-port RAM (1 address : 1 RW)
* High density type/High density partial write type Column type Memory capacity Word range 4 16 16 to 72 K 64 to 72 K 16 to 1 K 64 to 4 K Bit range 1 to 72 1 to 18 Unit bit bit
* Super high density type/Super high density partial write type Column type Memory capacity Word range 4 64 to 144 K 32 to 2 K
Bit range 2 to 72
Unit bit
* Large scale partial write type Column type Memory capacity 16 24 to 1152 K
Word range 4K to 16 K
Bit range 6 to 72
Unit bit
* Super high density large scale partial write type Column type Memory capacity Word range 16 * High speed type Column type 8 2 to 1152 K 512 to 16 K
Bit range 4 to 72
Unit bit
Memory capacity 256 to 144 K
Word range 64 to 2 K
Bit range 4 to 72
Unit bit
2. Clock synchronous dual-port RAM (2 addresses : 1 RW, 1 R)
* High density type/Partial write type Column type Memory capacity 4 16 16 to 72 K 64 to 72 K Word range 16 to 1 K 64 to 4 K Bit range 1 to 72 1 to 18 Unit bit bit
3. Clock synchronous register file (3 addresses : 1 W, 2 R)
Column type 1 Memory capacity 4 to 4608 Word range 4 to 64 Bit range 1 to 72 Unit bit
4. Clock synchronous register file (4 addresses : 2 W, 2 R)
Column type 1 Memory capacity 4 to 4608 Word range 4 to 64 Bit range 1 to 72 Unit bit
4
CS86 Series
5. Clock synchronous ROM (1 addresses : 1 R)
Column type 16 64 Memory capacity 256 to 1024 K 1 to 1024 K Word range 128 to 8 K 512 to 32 K Bit range 2 to 128 2 to 32 Unit bit bit
6. Clock synchronous delay line memory (2 addresses : 1 W, 1 R)
Column type 8 16 32 Memory capacity 256 to 32 K 384 to 32 K 512 to 32 K Word range 32 to 1 K 64 to 2 K 128 to 4 K Bit range 8 to 32 6 to 16 4 to 8 Unit bit bit bit
5
CS86 Series
s ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V) Parameter Supply voltage Input voltage Output voltage Storage temperature Junction temperature Output current*3 Input signal transmitting rate Output signal transmitting rate Output load capacitance Supply pin current Symbol VDD VI VO Tst Tj IO RI RO CO ID Rating Min - 0.5 - 0.5 - 0.5 -55 -40 7.5 (1.8 VCMOS) Clock input*4 : 200 Normal input : 100 100 3000/RO Max 2.5 *1 4.0 *2 VDD+0.5 ( 2.5 V) *1 VDD+0.5 ( 4.0 V) *2 VDD+0.5 ( 2.5 V) *1 VDD+0.5 ( 4.0 V) *2 +125 +125 Unit V V V C C mA Mbps*5 Mbps*5 pF mA
10 (3.3 VCMOS, 2.5 VCMOS)
See "* Supply pin current for one VDD/GND pin (mA) "
*1 : Internal gate part in case of single power supply or dual power supply *2 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply. *3 : DC current which continues more than 10 ms, or average DC current *4 : in case of I/O cell for clock input *5 : bps = bit per second * Supply pin current value for one VDD/GND pin (mA) (a) Maximum current for one I/O*1 Frame Source type VDDE VDDE YH VDDE VDDI, VDD, VSS VDDI, VDD, VSS VDDI, VDD, VSS Tj = +125 C*2 Maximum current (at standard source) (mA) 68 59 59 68 93 118 Number of layers 4 5 6 4 5 6
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CS86 Series
(b) Current value that one I/O can provide to the core Frame
YH
Tj = +125C*2 Number of layers
4 5 6 34 34 59
Source type
VDDI, VDD, VSS VDDI, VDD, VSS VDDI, VDD, VSS
Maximum current (at standard source) (mA)
*1 : Maximum current for one I/O includes the supply current to the I/O part and the core part. *2 : The current values change according to the junction temperature. When the junction temperature is not +125C, multiply the value by the following coefficients. Tj = +111C to +125C : 1.0 Tj = + 91C to +110C : 1.4 Tj = + 90C : 2.8 Note : How to calculate the number of required supply pins In case of a frame with 6-layer wiring (2 power supplies) * Maximum current for one VDD/GND pin VDDE = 59 mA/pin calucurated using the value in "(a) Maximum supply pin current for one I/O" VDDI = VSS = 59 mA/pin calucurated using the value in "(b) Current value that one I/O can provide to the core" * Needed supply pin count (internal power supply/external power supply/VSS) : Ni/Ne/Ns DC internal maximum power-supply current : Iimax, DC external maximum power-supply current : Iemax Ni = Iimax/59mA, Ne = Iemax/59mA, Ns = Iimax/59mA + Iemax/59mA WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
7
CS86 Series
s RECOMMENDED OPERATING CONDITIONS
* Single power supply (VDD = 1.8 V 0.15 V) Parameter Supply voltage "H" level input voltage "L" level input voltage Junction temperature Symbol VDD VIH VIL Tj Value Min 1.65 VDD x 0.65 -0.3 -40 Typ 1.8 Max 1.95 VDD + 0.3 VDD x 0.35 +125 (VSS = 0 V) Unit V V V C
* Dual power supply (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V/VDDI = 1.5 V 0.1 V/VDDI = 1.1 V 0.1 V*) (VSS = 0 V) Parameter Symbol VDDE Supply voltage VDDI 1.8 V CMOS 3.3 V CMOS 1.8 V CMOS 3.3 V CMOS Value Min 3.0 1.65 1.4 1.0 "H" level input voltage "L" level input voltage Junction temperature * : VDDI = 1.1 V0.1 V is being prepared. * Dual power supply (VDDE = 2.5 V 0.2 V, VDDI = 1.8 V 0.15 V/VDDI = 1.5 V 0.1 V/VDDI = 1.1 V 0.1 V*) (VSS = 0 V) Parameter Symbol VDDE Supply voltage VDDI 1.8 V CMOS 2.5 V CMOS 1.8 V CMOS 2.5 V CMOS Value Min 2.3 1.65 1.4 1.0 "H" level input voltage "L" level input voltage Junction temperature * : VDDI = 1.1 V0.1 V is being prepared. VIH VIL Tj VDDI x 0.65 1.7 -0.3 -0.3 -40 Typ 2.5 1.8 1.5 1.1 Max 2.7 1.95 1.6 1.2 VDDI + 0.3 VDDE + 0.3 VDDI x 0.35 0.7 +125 V V C V Unit VIH VIL Tj VDDI x 0.65 2.0 -0.3 -0.3 -40 Typ 3.3 1.8 1.5 1.1 Max 3.6 1.95 1.6 1.2 VDDI + 0.3 VDDE + 0.3 VDDI x 0.35 0.8 +125 V V C V Unit
8
CS86 Series
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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CS86 Series
s ELECTRICAL CHARACTERISTICS
1. DC characteristics
* Single power supply : VDD = 1.8 V standard Parameter "H" level output voltage "L" level output voltage "H" level output V-I characteristics "L" level output V-I characteristics Input leakage current Pull up/Pull down resistance Symbol VOH VOL IL RP (VDD = 1.8 V 0.15 V, VSS = 0 V, Tj = -40 C to +125 C) Conditions IOH = -100 A IOL = 100 A 1.8 V VDD = 1.8 V0.15 V 1.8 V VDD = 1.8 V0.15 V Pull up VIL = 0, Pull down VIH = VDD 8 Value Min VDD-0.2 0 Typ * * 18 5 40 Max VDD 0.2 Unit V V A k
* : Refer to " (1) 1.8 V" in sV-I CHARACTERISTICS. * Dual power supply : VDDE = 3.3 V, VDDI = 1.8 V/1.5 V/1.1 V (VDDE = 3.3 V0.3 V/VDDI = 1.8 V 0.15 V, VDDI = 1.5 V 0.1 V, VDDI = 1.1 V 0.1 V, VSS = 0 V, Tj = -40 C to +125 C) Parameter "H" level output voltage "L" level output voltage "H" level output V-I characteristics "L" level output V-I characteristics Input leakage current Symbol VOH4 VOH2 VOL4 VOL2 IL Conditions 3.3 V Output IOH = -100 A 1.8 V Output IOH = -100 A 3.3 V Output IOL = 100 A 1.8 V Output IOL = 100 A 3.3 V VDDE = 3.3 V0.3 V 1.8 V VDDI = 1.8 V0.15 V 3.3 V VDDE = 3.3 V0.3 V 1.8 V VDDI = 1.8 V0.15 V 3.3 V Pull up VIL = 0, Pull down VIH = VDDI 1.8 V Pull up VIL = 0, Pull down VIH = VDDI 10 Value Min VDDE-0.2 VDDI-0.2 0 0 Typ *1 *2 *1 *2 33 5 80 k 8 18 40 Max VDDE VDDI 0.2 0.2 Unit V V A
Pull up/Pull down resistance
RP
*1 : Refer to " (2) 3.3 V" in sV-I CHARACTERISTICS. *2 : Refer to " (1) 1.8 V" in sV-I CHARACTERISTICS.
10
CS86 Series
* Dual power supply : VDDE = 2.5 V, VDDI = 1.8 V/1.5 V/1.1 V (VDDE = 2.5 V0.2 V, VDDI = 1.8 V 0.15 V/VDDI = 1.5 V 0.1 V/VDDI = 1.1 V 0.1 V, VSS = 0 V, Tj = -40 C to +125 C) Parameter "H" level output voltage "L" level output voltage "H" level output V-I characteristics "L" level output V-I characteristics Input leakage current Symbol VOH3 VOH2 VOL3 VOL2 IL Conditions 2.5 V Output IOH = -100 A 1.8 V Output IOH = -100 A 2.5 V Output IOL = 100 A 1.8 V Output IOL = 100 A 2.5 V VDDE = 2.5 V0.2 V 1.8 V VDDI = 1.8 V0.15 V 2.5 V VDDE = 2.5 V0.2 V 1.8 V VDDI = 1.8 V0.15 V 2.5 V Pull up VIL = 0, Pull down VIH = VDDE 1.8 V Pull up VIL = 0, Pull down VIH = VDDI Value Min VDDE-0.2 VDDI-0.2 0 0 Typ * * 25 5 k 8 18 40 Max VDDE VDDI 0.2 0.2 Unit V V A
Pull up/Pull down resistance
RP
* : Refer to " (1) 1.8 V" in sV-I CHARACTERISTICS.
2. AC CHARACTERISTICS
Parameter Delay time Symbol tpd*
1
Min
2
VSS = 0 V, Tj = - 40 C to +125 C. (Standard specification) Value Unit Typ Max typ*2 x ttyp*3 typ*2 x tmax*3 ns
typ* x tmin*3
*1 : Delay time = propagation delay time, enable time, disable time. *2 : "typ" is calculated based on the cell specifications. *3 : Measurement conditions Measurement condition VDD = 1.8 V 0.15 V, VSS = 0 V, Tj = -40 C to +125 C VDD = 1.5 V 0.10 V, VSS = 0 V, Tj = -40 C to +125 C VDD = 1.1 V 0.1 V, VSS = 0 V, Tj = -40 C to +125 C tmin 0.62 0.76 1.08 ttyp 1.00 1.25 2.14 tmax 1.88 2.42 6.22
Note : AC characteristics are determined based on junction temperature, voltage conditions, and process variation.
11
CS86 Series
s V - I CHARACTERISTICS
(1) 1.8 V Conditions Min : Process = Slow, Tj = +125 C, VDD = 1.65 V Typ : Process = Typical, Tj = +25 C, VDD = 1.80 V Max : Process = Fast, Tj = -40 C, VDD = 1.95 V
-2.0
VOH-VDD (V) -1.0
0.0 0
40 Max 30 Typ IOL (mA) IOH (mA) 20 Min 10
-10 Min -20 Typ -30 Max -40
0 0.0
1.0 VOL (V)
2.0
1.8 V CMOS "H" level output (L, M type)
1.8 V CMOS "L" level output (L, M type)
-2.0
VOH-VDD (V) -1.0
0.0 0 -10
60 50 40 IOL (mA) Max
Min
-20 -30 -40 IOH (mA)
Typ 30 20 10 Min
Typ
Max
-50 -60 0 0.0 1.0 VOL (V) 2.0
1.8 V CMOS "H" level output (H, V type)
1.8 V CMOS "L" level output (H, V type)
12
CS86 Series
(2) 3.3 V Conditions Min : Process = Slow, Tj = +125 C, VDDE = 3.0 V Typ : Process = Typical, Tj = +25 C, VDDE = 3.3 V Max : Process = Fast, Tj = -40 C, VDDE = 3.6 V
-4.0
-3.0
VOH-VDDE (V) -1.0 -2.0
0.0 0
80 Max
-20 Min IOH (mA) IOL (mA) -40 Typ -60 Max -80
60 Typ 40 Min
20
0 0.0
1.0
2.0 VOL (V)
3.0
4.0
3.3 V CMOS "H" level output (L, M type)
3.3 V CMOS "L" level output (L, M type)
-4.0
VOH-VDDE (V) -2.0 -1.0 -3.0
0.0 0 -20 -40 IOH (mA) -60 IOL (mA)
120 Max 100 80 60 Min 40 20 0 0.0
Min
Typ
Typ -80 Max -100 -120
1.0
2.0 VOL (V)
3.0
4.0
3.3 V CMOS "H" level output (H, V type)
3.3 V CMOS "L" level output (H, V type)
13
CS86 Series
s INPUT/OUTPUT PIN CAPACITANCE
(Tj = +25 C, VDD = VI = 0 V, f = 1 MHz) Parameter Input pin Output pin I/O pin L, M, H, V type L, M, H, V type Symbol CIN COUT CI/O Requirements Max 16 Max 16 Max 16 Unit pF pF pF
Note : Capacitance varies according to the package and the location of the pin.
s DESIGN METHOD
The integrated standard-cell design environment, SCCAD2, provided for conventional models now supports the CS86 series. This allows you to design ASICs that operate at up to 500 MHz with up to 40 million gates and to halve the layout design period. The Fujitsu's tool GLOSCAD also supports the satandard cell design for CS86 series. * Physical Synthesis Physical Synthesis tool support is provided on a consulting business basis. A conventional style of ASIC development has a problem that iterations between logic synthesis and layout processing are caused by wiring congestion and the difference between actual and estimated wiring capacities. Supporting logic synthesis based on physical information reduces such iterations and contributes to convergence of ASIC design within the scheduled development period. * Low Power Synthesis The Low Power Synthesis tool is supported, which enables the use of gated clock buffers of hard macro type incorporating sequential cells, such as latches. The use of gated clock buffers of hard macro type provides low power consumption by the clock line. It also provides reliable operation, reduction in script complexity, and shorter turnaround time (TAT) for processing. * Timing Driven Layout Performing automatic placement and wiring based on chip-level timing constraints. This prevents post-layout timing problems from developing, which are prominent in particular in the field of deep submicron designs. In addition, all of remaining timing errors are automatically corrected by the Fujitsu's automatic timing correction system. This shortens the development time from the end of creating a net list to the beginning of the prototyping stage. * Hierarchical Design A top-down hierarchical design approach is taken consistently from logic design to physical design to support larger-scale circuit integration based on deep submicron designing. This enables multiple blocks to be designed logically and physically at the same time and timing convergence to be attained in a short period, providing a design environment capable of easily supporting ultra-large-scale integration of circuits. * Support for Signal Integrity Automated power wiring enables layout satisfying the design specifications within a short period. The power width automatic adjustment function designed taking account of internal power consumption and clock frequencies can produce chips satisfying the current density and voltage drop restrictions without human intervention. Also, a verification system is prepared to check the signal noise or delay penalty owing to capacitive coupling between signal conductors and the voltage drop caused by simultaneous local switching. 14
CS86 Series
s PACKAGES
Package QFP TQFP LQFP HQFP PBGA FBGA FLGA EBGA 176, 208, 240 100, 120 144, 176, 208, 256 208, 240, 256, 304 256, 352, 420 112, 144, 168, 176, 192, 224, 240, 272, 288, 304, 368 144, 176, 208, 224, 288 660 Pin count Material Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic
Note : Consult Fujitsu for the combination of each package and the time of availability.
15
CS86 Series
FUJITSU LIMITED
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F0312 (c) FUJITSU LIMITED Printed in Japan

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